Forming fins of different materials on the same substrate

ABSTRACT

A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer.

BACKGROUND

The present invention relates to semiconductor devices, and particularlyto methods of forming fins of two different semiconductor materials onthe same substrate.

Fin field effect transistors (FinFETs) are an emerging technology whichmay provide solutions to field effect transistor (FET) scaling problemsat, and below, the 22 nm node. FinFET structures may include at least anarrow semiconductor fin gated on at least two sides of each of thesemiconductor fin, as well as a source region and a drain regionadjacent to the fin on opposite sides of the gate. FinFET structureshaving n-type source and drain regions may be referred to as nFinFETs,and FinFET structures having p-type source and drain regions may bereferred to as pFinFETs.

In some FinFET structures, different materials may be used for the finsof pFinFETs and nFinFETs in order to improve device performance.However, a material that may improve pFinFET performance may reduce nFETperformance, and vice versa. For example, while pFinFET performance maybe improved by forming fins made of silicon-germanium, nFinFETperformance may instead be improved by forming fins made of carbon-dopedsilicon and may be degraded by forming fins made of silicon-germanium.Further, pFinFETs and nFinFETs are often fabricated on the samesubstrate.

SUMMARY

An embodiment of the invention may include a method of forming asemiconductor substrate by providing an providing asemiconductor-on-insulator (SOI) substrate including a basesemiconductor layer, a buried insulator layer above the basesemiconductor layer, and a SOI layer comprising a first semiconductormaterial above the buried insulator layer; forming an isolation regionin the SOI layer isolating a first portion of the SOI layer from asecond portion of the SOI layer; removing the second portion of the SOIlayer to expose a portion of the buried insulator layer; forming a holein the exposed portion of the buried insulator layer to expose a portionof the base semiconductor layer; and forming a semiconductor layer madeof a second semiconductor material on the exposed portion of the basesemiconductor layer, so that the replacement semiconductor layer coversthe exposed region of the buried insulator layer. In some embodiments,the first semiconductor material may be different from the secondsemiconductor material. Methods may further include etching the firstportion of the SOI layer to form a first fin made of the firstsemiconductor material and etching the semiconductor layer to form asecond fin made of the second semiconductor material.

In another embodiment of the invention, a semiconductor substrate mayinclude a base substrate layer; a buried a buried insulator layer abovethe base substrate layer; a first semiconductor layer above the buriedinsulator layer; and a second semiconductor layer above the buriedinsulator layer that contacts the base layer through a hole in theburied insulator layer.

In another embodiment of the invention, a semiconductor structure mayinclude a base substrate layer; a buried insulator layer above the basesubstrate layer; a first plurality of semiconductor fins on the buriedinsulator layer; and a second plurality of semiconductor fins on theburied insulator layer, at least one of which contacts the basesubstrate through a hole in the buried insulator layer.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a side view depicting a semiconductor-on-insulator (SOI)substrate, according to an embodiment of the present invention;

FIG. 2 is a side view depicting forming an isolation region in the SOIlayer of the SOI substrate, according to an embodiment of the presentinvention;

FIG. 3 is a side view depicting masking a first semiconductor region ofthe SOI layer adjacent to the isolation region, according to anembodiment of the present invention;

FIG. 4 is a side view depicting removing the unmasked portion of the SOIlayer, according to an embodiment of the present invention;

FIG. 5 is a side view depicting forming a hole in the insulating layerof the SOI substrate, according to an embodiment of the presentinvention;

FIG. 6 is a side view depicting growing a second semiconductor regionabove the insulating layer of the SOI substrate, according to anembodiment of the present invention;

FIG. 7 is a side view depicting planarizing the semiconductor region,according to an embodiment of the present invention; and

FIG. 8 is a side view depicting forming fins from the firstsemiconductor region and the second semiconductor region, according toan embodiment of the present invention.

Elements of the figures are not necessarily to scale and are notintended to portray specific parameters of the invention. For clarityand ease of illustration, dimensions of elements may be exaggerated. Thedetailed description should be consulted for accurate dimensions. Thedrawings are intended to depict only typical embodiments of theinvention, and therefore should not be considered as limiting the scopeof the invention. In the drawings, like numbering represents likeelements.

DETAILED DESCRIPTION

Exemplary embodiments now will be described more fully herein withreference to the accompanying drawings, in which exemplary embodimentsare shown. This disclosure may, however, be embodied in many differentforms and should not be construed as limited to the exemplaryembodiments set forth herein. Rather, these exemplary embodiments areprovided so that this disclosure will be thorough and complete and willfully convey the scope of this disclosure to those skilled in the art.In the description, details of well-known features and techniques may beomitted to avoid unnecessarily obscuring the presented embodiments

Embodiments may include methods of preparing a semiconductor substrateso that a semiconductor-on-insulator (SOI) substrate has a top layermade of two different semiconductor regions. The method may includeforming a isolation region in the SOI layer of the SOI substrate todivide the SOI layer into a first portion and a second portion (FIG. 2),removing the second portion of the SOI layer (FIG. 4), etching a hole inthe buried insulator layer beneath the removed second portion of the SOIlayer to exposed the base substrate (FIG. 5), and growing asemiconductor region on the base substrate to replace the second portionof the SOI layer (FIG. 6). By forming the semiconductor region of adifferent material than the SOI layer, the SOI substrate may then have atop layer formed by both a first semiconductor material on one side ofthe isolation region and a second semiconductor material on the otherside of the isolation region. The SOI substrate may then be used tofabricate any number of microelectronic devices where such adual-material substrate would be desirable. For example, a finFET devicemay be fabricated including both nFETs and pFETs, where the nFETs havesilicon fins and the pFETs have silicon-germanium fins.

For purposes of the description hereinafter, terms such as “upper”,“lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the disclosed structures andmethods, as oriented in the drawing figures. Terms such as “above”,“overlying”, “atop”, “on top”, “positioned on” or “positioned atop” meanthat a first element, such as a first structure, is present on a secondelement, such as a second structure, wherein intervening elements, suchas an interface structure may be present between the first element andthe second element. The term “direct contact” means that a firstelement, such as a first structure, and a second element, such as asecond structure, are connected without any intermediary conducting,insulating or semiconductor layers at the interface of the two elements.

In the interest of not obscuring the presentation of embodiments of thepresent invention, in the following detailed description, someprocessing steps or operations that are known in the art may have beencombined together for presentation and for illustration purposes and insome instances may have not been described in detail. In otherinstances, some processing steps or operations that are known in the artmay not be described at all. It should be understood that the followingdescription is rather focused on the distinctive features or elements ofvarious embodiments of the present invention.

Referring to FIG. 1, a SOI substrate 100 may include a basesemiconductor layer 110, a buried insulator layer 120, and an SOI layer130. The buried insulator layer 120 may isolate the SOI layer 130 fromthe base semiconductor layer 110. The base semiconductor layer 110 maybe made from any of several known semiconductor materials such as, forexample, silicon, germanium, silicon-germanium alloy, carbon-dopedsilicon, carbon-doped silicon-germanium alloy, and compound (e.g. III-Vand II-VI) semiconductor materials. Non-limiting examples of compoundsemiconductor materials include gallium arsenide, indium arsenide, andindium phosphide. In a preferred embodiment, the base semiconductorlayer 110 may include silicon, silicon-germanium, or carbon-dopedsilicon. Typically the base layer 110 may be approximately, but is notlimited to, several hundred microns thick. For example, the base layer110 may have a thickness ranging from approximately 0.5 mm toapproximately 1.5 mm.

The buried insulator layer 120 may be formed from any of severaldielectric materials. Non-limiting examples include, for example,oxides, nitrides, oxynitrides of silicon, and combinations thereof.Oxides, nitrides and oxynitrides of other elements are also envisioned.In addition, the buried insulator layer 120 may include crystalline ornon-crystalline dielectric material. The buried insulator layer 120 maybe 100-500 nm thick, preferably about 200 nm.

The SOI layer 130 may be made of any of the several semiconductormaterials possible for the base layer 110. In general, the base layer110 and the SOI substrate layer 130 may include either identical ordifferent semiconducting materials with respect to chemical composition,dopant concentration and crystallographic orientation. In a preferredembodiment, the SOI layer 130 comprises silicon, silicon-germanium, orcarbon-doped silicon. The SOI layer 130 may be doped with p-typedopants, such as boron, or doped with n-type dopants, such as phosphorusand/or arsenic. The dopant concentration may range from approximately1×10¹⁵ cm⁻³ to approximately 1×10¹⁹ cm⁻³, preferably approximately1×10¹⁵ cm⁻³ to approximately 1×10¹⁶ cm⁻³. In one embodiment, the SOIlayer is undoped. The SOI layer 130 may have a thickness ranging fromapproximately 5 nm to approximately 300 nm, preferably approximately 30nm.

Referring to FIG. 2, an isolation region 210 may be formed in the SOIlayer 130, so that the SOI layer 130 is divided into a first SOI portion135 and a second SOI portion 137. The isolation region 210 may be formedusing various methods known in the art. For example, a shallow trenchisolation (STI) process may be utilized. In a STI process, a trench maybe etched in the SOI layer 130, an insulating layer may be deposited tofill the trench, and the insulating layer is planarized to remove anyinsulating material from outside the trench (not shown). In otherembodiments, the first SOI portion 135 and the second SOI portion 137may be masked while dopants may be implanted into the isolation region210 so that the material of the SOI layer 130 in the isolation region210 is converted from semiconductive to insulating (not shown). Theisolation region 210 may also be formed using other suitable methods notexplicitly disclosed herein.

Referring to FIG. 3, the first SOI portion 135 may be masked by amasking layer 310. The masking layer 310 may be made of any suitablematerial capable of protecting the first SOI portion 135 during thesubsequent etch and epitaxial growth processes discussed below inconjunction with FIGS. 4-6. Particularly, the masking layer 310 may beheat resistant to withstand high temperatures required of some epitaxialgrowth processes, as well as being resistant to subsequent processesused to etch the buried insulator layer 120, as described below inconjunction with FIG. 5. In an exemplary embodiment, the masking layer310 may be made of oxides, nitrides, and oxynitrides of silicon, as wellas oxides, nitrides, and oxynitrides of silicon of other elements, andmay have a thickness of approximately 10 nm to approximately 10000 nm.In a preferred embodiment, the buried insulator layer 120 may be made ofsilicon nitride and have a thickness of approximately 50 nm toapproximately 500 nm.

Referring to FIG. 4, the second SOI portion 137 may be removed to forman exposed region of the buried insulator layer 120. The second SOIportion 137 may be removed using any suitable etching technique known inthe art, including both wet and dry etching techniques, as well asisotropic and anisotropic etching techniques. In a preferred embodiment,a wet etching technique may be used, for example a potassium hydroxidewet etch or a HNA (hydrofluoric acid, nitric acid, acetic acid) wetetch. Other methods of removing the second SOI portion 137 are known inthe art, including, for example, RIE etching and hydrogen chloride gasetching.

Referring to FIG. 5, a hole 410 may be formed in the buried insulatorlayer 120 to form an exposed region of the base semiconductor layer 110.The hole 410 may preferably be as small as possible while still allowingthe epitaxial growth process detailed below in conjunction with FIG. 6.In an exemplary embodiment, the hole 410 may be approximately round witha diameter w₁ of not less than approximately 10 nm. In anotherembodiment, the hole 410 may be a trench with a width w₁ of not lessthan approximately 10 nm.

The hole 410 may be formed using any typical isotropic etch process,including, for example, RIE or plasma etching. In an exemplaryembodiment (not shown), a photoresist layer may be deposited above theburied insulator layer 120, patterned to form a hole in the photoresistlayer, so that the hole in the photoresist layer has the same dimensionsas desired for the hole 410. The buried insulator layer 120 may then beetched beneath the hole in the photoresist layer. Other typicalphotolithography and etching techniques may also be utilized, including,for example, forming a planarization layer between the buried insulatorlayer 120 and the photoresist layer because of the uneven topography(i.e., the height difference between the exposed portion of the buriedinsulator layer 120 and the first SOI portion 135).

Referring to FIG. 6, a semiconductor layer 510 may be formed above theexposed region of the buried insulator layer 120 by growing an epitaxialsemiconductor layer on the exposed region of the base semiconductorlayer 110. The semiconductor layer 510 may have a thickness, measuredfrom the top surface of the buried insulator layer 120, at least equalto or greater than the thickness of the first SOI portion 135. Thesemiconductor layer 510 may be made of any the materials possible forthe SOI layer 130, including, for example, known semiconductor materialssuch as, for example, silicon, germanium, silicon-germanium alloy,carbon-doped silicon, carbon-doped silicon-germanium alloy, and compound(e.g. III-V and II-VI) semiconductor materials. In a preferredembodiment, the material of the semiconductor layer 510 is the same asthe material of the base semiconductor layer 110, but different from thefirst SOI portion 135. In other embodiments, the material of thesemiconductor layer 510 may be different from the base semiconductorlayer 110. In further embodiments, the material of the semiconductorlayer may be the same as the first SOI portion 135. In an exemplaryembodiment, the base semiconductor layer 110 and the semiconductor layer510 may be made of silicon, while the SOI layer 130 may be made ofsilicon-germanium.

The semiconductor layer 510 may be formed by utilizing any epitaxialgrowth or deposition process known in the art. The terms “epitaxialgrowth and/or deposition” and “epitaxially formed and/or grown” mean thegrowth of a semiconductor material on a deposition surface of asemiconductor material, in which the semiconductor material being grownhas the same crystalline characteristics as the semiconductor materialof the deposition surface. In an epitaxial deposition process, thechemical reactants provided by the source gases are controlled and thesystem parameters are set so that the depositing atoms arrive at thedeposition surface of the semiconductor substrate with sufficient energyto move around on the deposition surface and orient themselves to thecrystal arrangement of the atoms of the deposition surface. Therefore,an epitaxial semiconductor layer has the same crystallinecharacteristics as the deposition surface on which it is formed. Forexample, an epitaxial semiconductor material deposited on a {100}crystal surface will take on a {100} orientation. In some embodiments,epitaxial growth and/or deposition processes are selective to forming onsemiconductor surface, and do not deposit material on dielectricsurfaces, such as silicon dioxide or silicon nitride surfaces. Examplesof various epitaxial growth process apparatuses that are suitable foruse in forming the semiconductor layer 510 include, for example rapidthermal chemical vapor deposition (RTCVD), low-energy plasma deposition(LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD),atmospheric pressure chemical vapor deposition (APCVD) and molecularbeam epitaxy (MBE).

In an exemplary embodiment where the semiconductor layer 510 is made ofsilicon-germanium, a number of different source gases may be used. Inone embodiment, a combination of a silicon source gas and a germaniumsource gas may be used in forming the layer of silicon germanium alloy.Examples of silicon source gases that may be used include silane,disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane,dichlorosilane, trichlorosilane, methylsilane, dimethylsilane,ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane andcombinations thereof. Examples of germanium source gases that may beused include germane, digermane, halogermane, dichlorogermane,trichlorogermane, tetrachlorogermane and combinations thereof. In someembodiments, a single source gas that includes a silicon component and agermanium component may be used in forming the semiconductor layer 510.Carrier gases like hydrogen, nitrogen, helium and argon may be usedduring the epitaxial growth process.

In an exemplary embodiment where the semiconductor layer 510 is made ofcarbon-doped silicon, a carbon source gas may be added the siliconsource gas described above. Examples of carbon source gases that may beused in the present application include, for example, alkanes, alkenes,and alkynes.

Referring to FIG. 7, the semiconductor layer 510 may be planarized sothat the top surface of the semiconductor layer 510 is approximatelycoplanar with the top surface of the first SOI portion 135. Any suitableplanarization process may be used, including, for example,chemical-mechanical planarization (CMP). To ensure coplanarity, thefirst SOI portion 135 may be used as a planarization stop layer. Afterplanarization, the semiconductor layer 510 may have substantially thesame thickness as the first SOI portion 135

Referring to FIG. 8, a first plurality of fins 610 and a secondplurality of fins 620 may be formed from the first SOI portion 135 andthe semiconductor layer 510, respectively, so that the first pluralityof fins 610 are made of the material of the first SOI portion 135 andthe second plurality of fins 620 are made of the material of thesemiconductor layer 510. While the first plurality of fins 610 and thesecond plurality of fins 620 are each depicted as including 5 fins, eachmay include as few as one fin or more than 5 fins. Each of the firstplurality of fins 610 and the second plurality of fins 620 may have awidth of approximately 2 nm to approximately 100 nm, preferablyapproximately 4 nm to approximately 40 nm. Because of planarizationprocess described above in conjunction with FIG. 7, the first pluralityof fins 610 and the second plurality of fins 620 may have substantiallythe same height.

The first plurality of fins 610 and a second plurality of fins 620 maybe formed by removing material from the SOI layer 130 (FIGS. 1A-1D)using a photolithography process followed by an anisotropic etchingprocess such as reactive ion etching (RIE) or plasma etching. In otherembodiments, the first plurality of fins 610 and a second plurality offins 620 may be formed by any other process known in the art, including,for example, sidewall image transfer (SIT).

After forming the first plurality of fins 610 and a second plurality offins 620, further typical semiconductor fabrication processes mayperformed on the first plurality of fins 610 and a second plurality offins 620 to form a microelectronic device such as plurality of fin fieldeffect transistors (finFETs). A person of ordinary skill in the art willunderstand how an SOI substrate including a top semiconductor layer madeof a first semiconductor material and a second semiconductor materialmay be desirable in the fabrication of microelectronic devices otherthan finFETs.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiment, the practical application or technicalimprovement over technologies found in the marketplace, or to enableother of ordinary skill in the art to understand the embodimentsdisclosed herein. It is therefore intended that the present inventionnot be limited to the exact forms and details described and illustratedbut fall within the scope of the appended claims.

1. A method of forming a semiconductor substrate, the method comprising:providing a semiconductor-on-insulator (SOI) substrate comprising a basesemiconductor layer, a buried insulator layer above the basesemiconductor layer, and a SOI layer comprising a first semiconductormaterial above the buried insulator layer; forming an isolation regionin the SOI layer isolating a first portion of the SOI layer from asecond portion of the SOI layer; removing the second portion of the SOIlayer to expose a portion of the buried insulator layer; forming a holein the exposed portion of the buried insulator layer to expose a portionof the base semiconductor layer; and forming a semiconductor layercomprising a second semiconductor material on the exposed portion of thebase semiconductor layer and the exposed region of the buried insulatorlayer.
 2. The method of claim 1, wherein the first semiconductormaterial is different from the second semiconductor material.
 3. Themethod of claim 1, wherein the first semiconductor material and thesecond semiconductor material are selected from the group consisting ofsilicon, silicon-germanium, and carbon-doped silicon.
 4. The method ofclaim 1, wherein forming a semiconductor layer comprising a secondsemiconductor material comprises epitaxially growing the secondsemiconductor material on the exposed portion of the base substrate. 5.The method of claim 4, wherein the second semiconductor materialcomprises the same material as the base semiconductor layer.
 6. Themethod of claim 1, wherein forming a hole in the exposed portion of theburied insulator layer comprises etching a round hole in the buriedinsulator layer with a diameter of not less than approximately 10 nm. 7.The method of claim 1, wherein forming a hole in the exposed portion ofthe buried insulator layer comprises etching a trench with a width ofnot less than 10 nm in the buried insulator layer.
 8. The method ofclaim 1, further comprising: etching the first portion of the SOI layerto form a first fin made of the first semiconductor material; andetching the semiconductor layer to form a second fin made of the secondsemiconductor material.
 9. A semiconductor substrate comprising: a basesubstrate layer: a buried insulator layer above the base substratelayer; a first semiconductor layer above the buried insulator layer; asecond semiconductor layer above the buried insulator layerapproximately coplanar with the first semiconductor layer; wherein thesecond semiconductor layer contacts the base substrate layer through ahole in the buried insulator layer.
 10. The semiconductor substrate ofclaim 9, further comprising an isolation region separating the firstsemiconductor layer from the second semiconductor layer.
 11. Thesemiconductor substrate of claim 9, wherein the first semiconductorlayer is made of a different material than the second semiconductorlayer.
 12. The semiconductor substrate of claim 9, wherein the firstsemiconductor layer and the second semiconductor layer are made ofmaterials selected from the group consisting of silicon,silicon-germanium, and carbon-doped silicon.
 13. The semiconductorsubstrate of claim 9, wherein the hole is approximately round and has adiameter of no less than approximately 10 nm.
 14. The semiconductorsubstrate of claim 9, wherein the hole is a trench having a width of noless than approximately 10 nm.
 15. A semiconductor structure comprising:a base substrate layer; a buried insulator layer above the basesubstrate layer; a first plurality of semiconductor fins on the buriedinsulator layer; a second plurality of semiconductor fins on the buriedinsulator layer, wherein one or more of the second plurality of finscontacts the base substrate layer through a hole in the buried insulatorlayer.
 16. The semiconductor structure of claim 15, further comprisingan isolation region separating the first plurality of semiconductor finsfrom the second plurality of semiconductor fins.
 17. The semiconductorsubstrate of claim 15, wherein the first plurality of semiconductor finsis made of a different material than the second plurality ofsemiconductor fins.
 18. The semiconductor substrate of claim 17, whereinthe first plurality of semiconductor fins and the second plurality ofsemiconductor fins are made of materials selected from the groupconsisting of silicon, silicon-germanium, and carbon-doped silicon. 19.The semiconductor substrate of claim 15, wherein the hole isapproximately round and has a diameter of not less than approximately 10nm.
 20. The semiconductor substrate of claim 15, wherein the hole is atrench having a width, measured perpendicular to the first plurality offins and the second plurality of fins, of a diameter of not less thanapproximately 10 nm.